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Listar por autor "Núñez Martínez, Juan"
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Ponencia
Assessing application areas for tunnel transistor technologies
Avedillo de Juan, María José; Núñez Martínez, Juan (Institute of Electrical and Electronics Engineers (IEEE), 2016)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Ponencia
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Instituto Nacional de Astrofísica, Óptica y Electrónica; Universidad de Sevilla, 2012-03)The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an IV characteristic ...
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Artículo
Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
Núñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2016)In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors ...
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Artículo
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
Núñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Ponencia
Complementary tunnel gate topology to reduce crosstalk effects
Núñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers (IEEE), 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome ...
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Tesis Doctoral
Desarrollo y evaluación de arquitecturas lógicas basadas en Nanopipeline.
Quintero Álvarez, Héctor Javier (2018-07-17)El potencial de la lógica dinámica, con sus fases de precarga y evaluación es una solución muy estudiada y aplicada, para ...
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Artículo
Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
Núñez Martínez, Juan; Ginés Arteaga, Antonio José; Peralías Macías, Eduardo; Rueda Rueda, Adoración (Springer, 2016)This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low ...
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Artículo
Digital Implementation of Oscillatory Neural Network for Image Recognition Applications
Abernot, Madeleine; Gil, Thierry; Jiménez, Manuel; Núñez Martínez, Juan; Avedillo de Juan, María José; Linares Barranco, Bernabé; Gonos, Théophile; Hardelin, Tanguy; Todri Sanial, Aida (Frontiers Media, 2021)Computing paradigm based on von Neuman architectures cannot keep up with the ever-increasing data growth (also called “data ...
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Trabajo Fin de Máster
Diseño de una red neuronal oscilatoria digital con capacidad de aprendizaje on-line sobre FPGA
Vázquez Díaz, Daniel (2023)La inteligencia artificial es un concepto que cada vez está más integrado en nuestras vidas. Aunque no nos demos cuenta, ...
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Tesis Doctoral
Diseño lógico de circuitos digitales usando dispositivos con característica NDR
Núñez Martínez, Juan (2011-02-04)En esta tesis doctoral se han desarrollado técnicas de diseño para circuitos electrónicos integrados que empleen dispositivos ...
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Ponencia
DOE based high-performance gate-level pipelines
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintero Álvarez, Héctor Javier (Institute of Electrical and Electronics Engineers, 2014)Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in ...
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Artículo
Domino inspired MOBILE networks
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2012)MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ...
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Artículo
Efficient realisation of MOS-NDR threshold logic gates
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Wiley Open Access, 2009-11-05)A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms ...
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Ponencia
Efficient realization of RTD-CMOS logic gates
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (2011)The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit ...
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Artículo
Experimental Demonstration of Coupled Differential Oscillator Networks for Versatile Applications
Jiménez, Manuel; Núñez Martínez, Juan; Shamsi, Jafar; Linares Barranco, Bernabé; Avedillo de Juan, María José (Frontiers Media SA, 2023)Oscillatory neural networks (ONNs) exhibit a high potential for energy-efficient computing. In ONNs, neurons are implemented ...
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Artículo
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2014)Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable ...
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Ponencia
Exploring logic architectures suitable for TFETs devices
Núñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates ...
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Artículo
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs
Delgado Lozano, Ignacio María; Tena Sánchez, Erica; Núñez Martínez, Juan; Acosta Jiménez, Antonio José (IEEE, 2021)The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an ...
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Ponencia
Holding Dissapearance in RTD-based Quantizers
Núñez Martínez, Juan; Quintana Toledo, José María; Avedillo de Juan, María José (Laboratoire TIMA, 2007)Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition ...
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Artículo
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase
Todri Sanial, Aida; Carapezzi, Stefania; Delacour, Corentin; Abernot, Madeleine; Gil, Thierry; Corti, Elisabetta; Karg, Siegfried F.; Núñez Martínez, Juan; Jiménez, Manuel; Avedillo de Juan, María José; Linares Barranco, Bernabé (IEEE, 2022)Brain-inspired computing employs devices and architectures that emulate biological functions for more adaptive and ...